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DATA SHEET
MOS INTEGRATED CIRCUIT
PD780232
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The PD780232 is a member of the PD780232 Subseries in the 78K/0 Series. The PD780232 Subseries consists of products that incorporate a VFD controller/driver for panel control. A flash memory version, the PD78F0233, that can operate within the same power supply voltage range as the mask ROM version, and various development tools are also under development. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing.
PD780232 Subseries User's Manual:
U13364E
78K/0 Series User's Manual Instructions: U12326E
FEATURES
* I/O ports: 40 * Internal ROM and RAM * Internal ROM: * Internal high-speed RAM: * Internal buffer RAM: * VFD display RAM: 16 KB 768 bytes 32 bytes 112 bytes * VFD controller/driver: 53 display outputs (Universal grid supported) * 8-bit resolution A/D converter: 4 channels * Serial interface: 2 channels * Timer: 4 channels * Power supply voltage: VDD = 4.5 to 5.5 V
* Minimum instruction execution time can be changed from high speed (0.4 s) to low speed (6.4 s)
APPLICATIONS
Monolithic mini components, separated mini components, tuners, cassette tape decks, CD/MD players, audio amplifiers, etc.
ORDERING INFORMATION
Part Number Package 80-pin plastic QFP (14 x 14)
PD780232GC-xxx-8BT
Remark xxx indicates ROM code suffix.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. U13415EJ2V0DS00 (2nd edition) Date Published May 2001 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
2000 1998
PD780232
78K/0 SERIES LINEUP
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names.
Products in mass production Products under development Y subseries products are compatible with I2C bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42-/44-pin
PD78075B PD78078 PD78070A PD780058 PD78058F PD78054 PD780065 PD780078 PD780034A PD780024A PD78014H PD78018F PD78083
Inverter control
EMI-noise reduced version of the PD78078
PD78078Y PD78070AY PD780018AY PD780058Y PD78058FY PD78054Y
PD78054 with added timer and enhanced external interface
ROMless version of the PD78078 PD78078Y with enhanced serial I/O and limited function
PD78054 with enhanced serial I/O
EMI-noise reduced version of the PD78054
PD78018F with added UART and D/A converter and enhanced I/O PD780024A with expanded RAM capacity PD780034A with added timer and enhanced serial I/O PD780078Y PD780034AY PD780024A with enhanced A/D converter PD780024AY PD78018F with enhanced serial I/O EMI-noise reduced version of the PD78018F PD78018FY
Basic subseries for control On-chip UART, capable of operating at low voltage (1.8 V)
64-pin
PD780988
VFD drive
On-chip inverter controller and UART. EMI-noise reduced.
100-pin 78K/0 Series 80-pin 80-pin 80-pin
PD780208 PD780232 PD78044H PD78044F
LCD drive
PD78044F with enhanced I/O and VFD C/D. Display output total: 53
For panel control. On-chip VFD C/D. Display output total: 53
PD78044F with added N-ch open-drain I/O. Display output total: 34
Basic subseries for VFD drive. Display output total: 34
120-pin 120-pin 120-pin 100-pin 100-pin 100-pin
PD780338 PD780328 PD780318 PD780308 PD78064B PD78064
PD780308 with enhanced display capacity and timer. Segment signal output: 40 pins max. PD780308 with enhanced display capacity and timer. Segment signal output: 32 pins max. PD780308 with enhanced display capacity and timer. Segment signal output: 24 pins max.
PD780308Y PD78064Y
PD78064 with enhanced SIO, and expanded ROM, RAM capacity EMI-noise reduced version of the PD78064
Basic subseries for LCD drive, on-chip UART
Bus interface supported 100-pin 80-pin 80-pin 80-pin Meter control 100-pin 80-pin 80-pin
PD780948 PD78098B PD780701Y PD780833Y
On-chip DCAN controller PD78054 with added IEBusTM controller. EMI-noise reduced. On-chip DCAN/IEBus controller On-chip controller compliant with J1850 (Class 2)
PD780958 PD780852 PD780824
For industrial meter control On-chip automobile meter controller/driver For automobile meter driver. On-chip DCAN controller
Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some documents, but the functions of the two are the same.
2
Data Sheet U13415EJ2V0DS
PD780232
The major functional differences among the subseries are shown below.
Function Subseries Name Control ROM Capacity Timer 8-Bit 10-Bit 8-Bit A/D - D/A 2 ch 3 ch (UART: 1 ch) 88 Serial Interface I/O VDD External MIN. Expansion Value 1.8 V
8-Bit 16-Bit Watch WDT A/D 1 ch 1 ch 1 ch 8 ch
PD78075B 32 K to 40 K 4 ch PD78078 PD78070A
48 K to 60 K -
61 3 ch (time-division UART: 1 ch) 3 ch (UART: 1 ch) 68 69
2.7 V 1.8 V 2.7 V 2.0 V
PD780058 24 K to 60 K 2 ch PD78058F 48 K to 60 K PD78054
16 K to 60 K - 2 ch 1 ch 8 ch - - 8 ch
PD780065 40 K to 48 K PD780078 48 K to 60 K
PD780034A 8 K to 32 K PD780024A
4 ch (UART: 1 ch) 3 ch (UART: 2 ch) 3 ch (UART: 1 ch)
60 52 51
2.7 V 1.8 V
PD78014H PD78018F 8 K to 60 K PD78083
Inverter control VFD drive 8 K to 16 K - - - 1 ch - 8 ch -
2 ch
53
1 ch (UART: 1 ch) 3 ch (UART: 2 ch)
33 47 4.0 V
- -
PD780988 16 K to 60 K 3 ch Note PD780208 32 K to 60 K 2 ch PD780232 16 K to 24 K 3 ch PD78044H 32 K to 48 K 2 ch PD78044F 16 K to 40 K
1 ch - 1 ch
1 ch - 1 ch
1 ch
8 ch 4 ch 8 ch
-
-
2 ch
74 40
2.7 V 4.5 V 2.7 V
1 ch 2 ch
68
LCD drive
PD780338 48 K to 60 K 3 ch PD780328 PD780318 PD780308 48 K to 60 K 2 ch PD78064B 32 K PD78064
16 K to 32 K
2 ch
1 ch
1 ch
-
10 ch 1 ch 2 ch (UART: 1 ch)
54 62 70
1.8 V
-
1 ch
8 ch
-
-
3 ch (time-division UART: 1 ch) 2 ch (UART: 1 ch)
57
2.0 V
Bus PD780948 60 K 2 ch interface supported PD78098B 40 K to 60 K Meter control Dashboard control
2 ch 1 ch 2 ch
1 ch
1 ch
8 ch
-
- 2 ch
3 ch (UART: 1 ch)
79 69
4.0 V 2.7 V 2.2 V
- -
PD780958 48 K to 60 K 4 ch PD780852 32 K to 40 K 3 ch PD780824 32 K to 60 K
-
1 ch
-
-
-
2 ch (UART: 1 ch)
69
1 ch
1 ch
1 ch
5 ch
-
-
3 ch (UART: 1 ch) 2 ch (UART: 1 ch)
56 59
4.0 V
-
Note
16-bit timer: 2 channels 10-bit timer: 1 channel
Data Sheet U13415EJ2V0DS
3
PD780232
FUNCTION OVERVIEW
Item Internal memory ROM High-speed RAM Buffer RAM VFD display RAM General-purpose register Minimum instruction execution time Instruction set I/O ports 16 KB 768 bytes 32 bytes 112 bytes 8 bits x 32 registers (8 bits x 8 registers x 4 banks) * On-chip minimum instruction execution time variable function * 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s (@ 5.0 MHz operation with system clock) * Multiply/divide (8 bits x 8 bits, 16 bits / 8 bits) * Bit manipulation (set, reset, test, Boolean operation) Total: 40 Function
(including alternate-function pins for VFD) * CMOS I/Os: 11 * P-ch open-drain I/Os: 13 * P-ch open-drain outputs: 16 VFD controller/driver Total of display outputs: 53 * 15 mA display current: 20 * 5 mA display current: 33 * 8-bit resolution x 4 channels * Power supply voltage: AVDD = 4.5 to 5.5 V * 3-wire serial mode (automatic transmit/receive function): 1 channel * 2-wire serial mode (transmit only): 1 channel * 8-bit remote control timer: 1 channel * 8-bit timer: 2 channels * Watchdog timer: Vectored interrupt sources Maskable Non-maskable Software Power supply voltage Package Internal: 10, external: 2 Internal: 1 1 VDD = 4.5 to 5.5 V 80-pin plastic QFP (14 x 14) 1 channel
A/D converter Serial interface Timer
4
Data Sheet U13415EJ2V0DS
PD780232
CONTENTS 1. 2. 3. PIN CONFIGURATION (TOP VIEW) ................................................................................................. 6 BLOCK DIAGRAM ............................................................................................................................. 8 PIN FUNCTIONS ................................................................................................................................ 9
3.1 3.2 3.3 Port Pins ..................................................................................................................................................... 9 Non-Port Pins .......................................................................................................................................... 10 Pin I/O Circuits and Recommended Connection of Unused Pins ................................................... 11
4. 5.
MEMORY SPACE ............................................................................................................................. 13 PERIPHERAL HARDWARE FUNCTION FEATURES ................................................................... 14
5.1 5.2 5.3 5.4 5.5 5.6 Port ............................................................................................................................................................ 14 Clock Generator ...................................................................................................................................... 15 Timer/Event Counter ............................................................................................................................... 15 A/D Converter .......................................................................................................................................... 18 Serial Interface ........................................................................................................................................ 18 VFD Controller/Driver ............................................................................................................................. 19
6. 7. 8. 9.
INTERRUPT FUNCTIONS ............................................................................................................... 21 STANDBY FUNCTION ..................................................................................................................... 24 RESET FUNCTION ........................................................................................................................... 24 MASK OPTION ................................................................................................................................. 24
10. INSTRUCTION SET .......................................................................................................................... 25 11. ELECTRICAL SPECIFICATIONS .................................................................................................... 28 12. PACKAGE DRAWING ...................................................................................................................... 42 13. RECOMMENDED SOLDERING CONDITIONS .............................................................................. 43 APPENDIX A. DEVELOPMENT TOOLS ............................................................................................... 44 APPENDIX B. RELATED DOCUMENTS .............................................................................................. 47
Data Sheet U13415EJ2V0DS
5
PD780232
1. PIN CONFIGURATION (TOP VIEW)
* 80-pin plastic QFP (14 x 14)
PD780232GC-xxx-8BT
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VDD1 VSS1 X1 X2 IC RESET P27/SCK1 P26/SI1 P25/SO1 P24/BUSY P23 P22 P21/SO3 P20/SCK3 P00/INTP0 P01/INTP1 P02/TI AVSS ANI3 ANI2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VLOAD VDD2 FIP20 FIP21 FIP22 FIP23 FIP24/P30 FIP25/P31 FIP26/P32 FIP27/P33 FIP28/P34 FIP29/P35 FIP30/P36 FIP31/P37 FIP32/P40 FIP33/P41 FIP34/P42 FIP35/P43 FIP36/P44 FIP37/P45
Cautions 1. Connect directly the IC (Internally Connected) pin to VSS1. 2. Connect the AVDD pin to VDD1. 3. Connect the AVSS pin to VSS1. Remark When the PD780232 is used in application fields that require reduction of the noise from inside the microcontroller, the implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended.
6
ANI1 ANI0 VSS0 AVDD VDD0 P64/FIP52 P63/FIP51 P62/FIP50 P61/FIP49 P60/FIP48 P57/FIP47 P56/FIP46 P55/FIP45 P54/FIP44 P53/FIP43 P52/FIP42 P51/FIP41 P50/FIP40 P47/FIP39 P46/FIP38
Data Sheet U13415EJ2V0DS
FIP0 FIP1 FIP2 FIP3 FIP4 FIP5 FIP6 FIP7 FIP8 FIP9 FIP10 FIP11 FIP12 FIP13 FIP14 FIP15 FIP16 FIP17 FIP18 FIP19
PD780232
ANI0 to ANI3: AVDD: AVSS: BUSY: FIP0 to FIP52: IC: INTP0, INTP1 P00 to P02: P20 to P27: P30 to P37: P40 to P47: Analog input Analog power supply Analog ground Busy Fluorescent indicator panel Internally connected External interrupt input Port 0 Port 2 Port 3 Port 4 P50 to P57: P60 to P64: RESET: SI1: SO1, SO3: TI: VDD0 to VDD2: VLOAD: VSS0, VSS1: X1, X2: Port 5 Port 6 Reset Serial input Serial output Timer input Power supply Negative power supply Ground Crystal
SCK1, SCK3: Serial clock
Data Sheet U13415EJ2V0DS
7
PD780232
2. BLOCK DIAGRAM
Port 0 TI/P02 8-bit remote controller timer 9
P00 to P02
Port 2
P20 to P27
Port 3 8-bit timer 80 78K/0 CPU core 8-bit timer 81 Port 5 Watchdog timer Port 6 SCK3/P20 SO3/P21 Serial interface (2-wire mode) ROM 16 KB Port 4
P30 to P37
P40 to P47
P50 to P57
P60 to P64
RAM 768 bytes
FIP0 to FIP23 FIP24/P30 to FIP31/P37 VFD controller/ driver FIP32/P40 to FIP39/P47 FIP40/P50 to FIP47/P57 FIP48/P60 to FIP52/P64 VLOAD VDD2
BUSY/P24 SO1/P25 SI1/P26 SCK1/P27 Serial interface (3-wire mode)
ANI0 to ANI3 AVDD AVSS A/D converter (A/D1)
INTP0/P00 INTP1/P01
Interrupt control (INT)
VDD0, VDD1
VSS0, VSS1
VPP
System control
RESET X1 X2
8
Data Sheet U13415EJ2V0DS
PD780232
3. PIN FUNCTIONS
3.1 Port Pins
After Reset Input Alternate Function INTP0 INTP1 TI Input SCK3 SO3 -- BUSY SO1 SI1 SCK1 Output Port 3. P-ch open-drain 8-bit high-tolerance output port. A pull-down resistor can be incorporated in 1-bit units to VLOAD by mask option. Port 4. P-ch open-drain 8-bit high-tolerance output port. A pull-down resistor can be incorporated in 1-bit units to VLOAD by mask option. Port 5. P-ch open-drain 8-bit high-tolerance I/O port. Input/output can be specified in 1-bit units. A pull-down resistor can be incorporated in 1-bit units by mask option (Connection to VLOAD or VSS0 can be specified in 1-bit units). Port 6. P-ch open-drain 5-bit high-tolerance I/O port. Input/output can be specified in 1-bit units. A pull-down resistor can be incorporated in 1-bit units by mask option (Connection to VLOAD or VSS0 can be specified in 1-bit units). Output FIP24 to FIP31
Pin Name P00 P01 P02 P20 P21 P22, P23 P24 P25 P26 P27 P30 to P37
I/O I/O
Function Port 0. 3-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by software. Port 2. 8-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by software.
I/O
P40 to P47
Output
Output
FIP32 to FIP39
P50 to P57
I/O
Input
FIP40 to FIP47
P60 to P64
I/O
Input
FIP48 to FIP52
Data Sheet U13415EJ2V0DS
9
PD780232
3.2 Non-Port Pins
After Reset Input Alternate Function P00 P01 Input Input Input Input Input Input Input Output P02 P20 P21 P24 P25 P26 P27 -- P30 to P37 P40 to P47 Input P50 to P57 P60 to P64
Pin Name INTP0 INTP1 TI SCK3 SO3 BUSY SO1 SI1 SCK1 FIP0 to FIP23 FIP24 to FIP31 FIP32 to FIP39 FIP40 to FIP47 FIP48 to FIP52
I/O Input
Function External interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 8-bit remote control timer 9 (TM9) timer input Serial interface serial clock input/output Serial interface serial data output Serial interface automatic transmit/receive busy signal input Serial interface serial data output Serial interface serial data input Serial interface serial clock input/output VFD controller/driver high-tolerance large current output. A pull-down resistor can be incorporated to VLOAD in 1-bit units by a mask option. VFD controller/driver high-tolerance large current output. A pull-down resistor can be incorporated in 1-bit units by a mask option (Connection to VLOAD or VSS0 can be specified in 1-bit units).
Input I/O Output Input Output Input I/O Output
VLOAD RESET X1 X2 ANI0 to ANI3 AVDD AVSS VDD0 VDD1 VDD2 VSS0 VSS1 IC
-- Input Input -- Input -- -- -- -- -- -- -- --
Connecting pull-down resistor for VFD controller/driver System reset input Connecting crystal resonator for system clock oscillation
-- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- --
A/D converter analog input A/D converter analog power supply/reference voltage input. Make the same potential as VDD1. A/D converter ground potential. Make the same potential as VSS1. Positive power supply for ports Positive power supply except for ports, analog block, and VFD controller/driver Positive power supply for VFD controller/driver Ground potential for ports Ground potential except for ports and analog block Internally connected. Connect directly to VSS1.
Input -- -- -- -- -- -- -- --
10
Data Sheet U13415EJ2V0DS
PD780232
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type of each pin and the recommended connection of unused pins are shown in Table 3-1. For the I/O circuit configuration of each type, see Figure 3-1. Table 3-1. Types of Pin I/O Circuits
Pin Name P00/INTP0 P01/INTP1 P02/TI P20/SCK3 P21/SO3 P22, P23 P24/BUSY P25/SO1 P26/SI1 P27/SCK1 P30/FIP24 to P37/FIP31 P40/FIP32 to P47/FIP39 P50/FIP40 to P57/FIP47 P60/FIP48 to P64/FIP52 FIP0 to FIP23 RESET ANI0 to ANI3 AVDD AVSS VLOAD IC Connect directly to VSS1. 14-F 2 7 -- -- Output Input Connect to VDD0 or VSS0. Connect to VDD1. Connect to VSS1. 15-D I/O Input: Independently connect to VDD0 or VSS0 via a resistor. Output: Leave open. Leave open. -- 14-F Output Leave open. Input: Independently connect to VDD0 or VSS0 via a resistor. Output: Leave open. I/O Circuit Type 8-C I/O I/O Recommended Connection of Unused Pins Input: Independently connect to VSS0 via a resistor. Output: Leave open.
Data Sheet U13415EJ2V0DS
11
PD780232
Figure 3-1. Pin I/O Circuits
Type 2 Type 14-F VDD0 VDD0
IN Data
P-ch
P-ch OUT
N-ch Schmitt-triggered input with hysteresis characteristics VSS0
Mask option VLOAD
Type 7
Type 15-D
VDD0 P-ch
VDD0 P-ch IN/OUT
Data IN P-ch N-ch Comparator
+ -
N-ch VSS0
VREF (threshold voltage) RD N-ch
Mask option VLOAD
VSS0 Type 8-C Pullup enable VDD0 Data P-ch IN/OUT Output disable VSS0 N-ch VDD0
VSS0
P-ch
12
Data Sheet U13415EJ2V0DS
PD780232
4. MEMORY SPACE
The memory map of the PD780232 is shown in Figure 4-1. Figure 4-1. Memory Map
F F F FH Special function registers (SFR) 256 x 8 bits F F 0 0H F E F F H General-purpose registers FEE 0H F ED F H
32 x 8 bits
Internal high-speed RAM 768 x 8 bits FC 0 0 H FB F FH Reserved FA 7 0H FA 6 FH Data memory space FA 0 0H F 9 F FH Reserved F 9E 0H F 9D F H Internal buffer RAM 32 x 8 bits F 9C 0 H F 9B FH Reserved 4 0 0 0H 3 F F FH 0 0 4 0H 0 0 3 FH Vector table area 0 0 0 0H 0 0 0 0H 0 0 8 0H 0 0 7 FH CALLT table area 0 8 0 0H 0 7 F FH Program area VFD display RAM 112 x 8 bits 1 0 0 0H 0 F F FH CALLF entry area
3 F F FH Program area
Program memory space
Internal ROM
Data Sheet U13415EJ2V0DS
13
PD780232
5. PERIPHERAL HARDWARE FUNCTION FEATURES
5.1 Port There are three kinds of I/O ports. * CMOS I/O (ports 0, 2): * P-ch open-drain I/O (ports 5, 6): Total: 11 13 40
* P-ch open-drain output (ports 3, 4): 16
Table 5-1. Port Functions
Name Port 0 Port 2 Port 3 Port 4 Port 5 Pin Name P00 to P02 P20 to P27 P30 to P37 P40 to P47 P50 to P57 Function I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip resistor can be specified by software. I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip resistor can be specified by software. P-ch open-drain high-tolerance output port. A pull-down resistor can be incorporated in 1-bit units to VLOAD by a mask option. P-ch open-drain high-tolerance output port. A pull-down resistor can be incorporated in 1-bit units to VLOAD by a mask option. P-ch open-drain high-tolerance I/O port. Input/output can be specified in 1-bit units. A pull-down resistor can be incorporated in 1-bit units by a mask option (Connection to VLOAD or VSS0 can be specified in 1-bit units ). P-ch open-drain high-tolerance I/O port. Input/output can be specified in 1-bit units. A pull-down resistor can be incorporated in 1-bit units by a mask option (Connection to VLOAD or VSS0 can be specified in 1-bit units).
Port 6
P60 to P64
14
Data Sheet U13415EJ2V0DS
PD780232
5.2 Clock Generator The minimum instruction execution time can be changed. * 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s (@ 5.0 MHz operation with main system clock) Figure 5-1. Clock Generator Block Diagram
Prescaler X1 X2 Main system clock oscillator
fX fX 2
Prescaler fX 22 fX 23 fX 24
Clock to peripheral hardware
STOP
Selector
Standby controller
CPU clock (fCPU)
5.3 Timer/Event Counter Four timer/event counter channels are incorporated. * 8-bit remote control timer: 1 channel * 8-bit timer: * Watchdog timer: 2 channels 1 channel
Table 5-2. Timer/Event Counter Operations
8-Bit Remote Control Timer Operation Interval timer mode Function Pulse width measurement Interrupt source -- 1 input 3 8-Bit Timer 2 channels -- 2 Watchdog Timer 1 channel -- 1
Data Sheet U13415EJ2V0DS
15
PD780232
Figure 5-2. Block Diagram of 8-Bit Remote Control Timer (TM9)
Internal bus INTTM90 TI/P02 Noise elimination rising edge detector fX/26 fX/27 fX/28 fX/29 Noise elimination falling edge detector 8-bit capture register 90 (CP90)
Selector
1/2
8-bit timer counter 9 (TM9)
INTTM92
INTTM91 8-bit capture register 91 (CP91)
Internal bus
Figure 5-3. Block Diagram of 8-Bit Timer (TM80)
fX fX/22 fX/24 fX/26
Selector/controller
8-bit timer counter 80 (TM80) Match INTTM80
8-bit compare register 80 (CR80)
Internal bus
16
Data Sheet U13415EJ2V0DS
PD780232
Figure 5-4. Block Diagram of 8-Bit Timer (TM81)
fX/2 fX/23 fX/25 fX/27
Selector/controller
8-bit timer counter 81 (TM81) Match INTTM81
8-bit compare register 81 (CR81)
Internal bus
Figure 5-5. Watchdog Timer Block Diagram
fX Clock input controller Divided clock selector
fX/28
Divider
Output controller
INTWDT RESET
RUN
Division mode selector
3 WDT mode signal
OSTS2 OSTS1 OSTS0
Oscillation stabilization time selection register (OSTS)
WDCS2 WDCS1 WDCS0
RUN WDTM4 WDTM3
Watchdog timer clock selection register (WDCS)
Watchdog timer mode register (WDTM)
Internal bus
Data Sheet U13415EJ2V0DS
17
PD780232
5.4 A/D Converter An 8-bit resolution 4-channel A/D converter is incorporated. A/D conversion can be started by software only. Figure 5-6. A/D Converter Block Diagram
INTAD ANI0 ANI1 ANI2 ANI3
Selector
Sample & hold circuit
A/D converter (8 bits)
A/D conversion result register (ADCR0)
Internal bus
5.5 Serial Interface Two clocked serial interface channels are incorporated. Serial interface SIO1 operates in the 3-wire serial mode (with automatic transmit/receive function), in which MSB first/LSB first switching is possible. Serial interface SIO3 operates in the 2-wire serial mode (transmit only) in which the first bit is fixed to MSB.
Figure 5-7. Serial Interface SIO1 Block Diagram
Internal bus
Automatic data transmit/receive address pointer (ADTP)
Buffer RAM
Automatic data transmit/receive transfer interval specification register (ADTI)
SI1/P26
Serial shift register 1 (SIO1)
Match
SO1/P25 5-bit counter Handshake controller BUSY/P24
SCK1/P27
Serial clock counter
Interrupt request signal generator
INTCSI1
Serial clock controller
18
Data Sheet U13415EJ2V0DS
Selector
fX/22 to fX/24
PD780232
Figure 5-8. Serial Interface SIO3 Block Diagram
Internal bus
Serial shift register 3 (SIO3)
SO3/P21
SCK3/P20
Serial clock counter
Interrupt request signal generator
INTCSI3
Selector
Serial clock controller
fX/22 to fX/24
5.6 VFD Controller/Driver A VFD controller/driver with the following functions is incorporated. (a) Total number of display outputs: 53. Output of 16 patterns is enabled. (b) 112-byte display RAM is provided to enable display signal output by reading display data automatically (direct memory access (DMA)). (c) A port pin that is not used for VFD display can be used as an output port or an I/O port (except for FIP0 to FIP23, which are VFD output-only pins). (d) The luminance can be adjusted in 8 levels using display mode register 1 (DSPM1). (e) Hardware taking into consideration the key scan application is incorporated. (f) Whether the key scan timing is inserted or not is selectable. (g) A high-tolerance output buffer (VFD driver) that can drive the VFD directly is incorporated. (h) VFD output pins can incorporate a pull-down resistor, set by a mask option.
Data Sheet U13415EJ2V0DS
19
PD780232
Figure 5-9. VFD Controller/Driver Block Diagram
Internal bus
Display data memory
Display data selector
Display data latch
Port output latch
High-tolerance buffer
FIP0
FIP24/P30
FIP52/P64
20
Data Sheet U13415EJ2V0DS
PD780232
6. INTERRUPT FUNCTIONS
There are 3 types of interrupt functions. * Non-maskable: 1 * Maskable: * Software: 12 1 Table 6-1. Interrupt Source List
Vector Table Address 0004H Basic Configuration TypeNote 2 (A) (B) External 0006H 0008H Remote control timer input rising edge detection Remote control timer input falling edge detection Remote control timer overflow Key scan timing from VFD controller/driver Serial interface SIO1 transfer end Serial interface SIO3 transfer end TM80 and CR80 match TM81 and CR81 match A/D conversion end BRK instruction execution -- Internal 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH 003EH (D) (B) (C)
Interrupt Type Nonmaskable Maskable
Default PriorityNote 1 -- 0 1 2 3 4 5 6 7 8 9 10 11 Name INTWDT INTWDT INTP0 INTP1 INTTM90 INTTM91 INTTM92 INTKS INTCSI1 INTCSI3 INTTM80 INTTM81 INTAD BRK
Interrupt Source Trigger Watchdog timer overflow (when watchdog timer mode 1 is selected) Watchdog timer overflow (when interval timer mode is selected) Pin input edge detection
Internal/ External Internal
Software
--
Notes 1. Default Priority is the priority order when more than one maskable interrupt request is generated simultaneously. 0 is the highest priority and 11 is the lowest. 2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 6-1.
Remark
Two watchdog timer interrupt sources (INTWDT) are available: a non-maskable interrupt and a maskable interrupt (internal), either of which can be selected.
Data Sheet U13415EJ2V0DS
21
PD780232
Figure 6-1. Basic Interrupt Function Configuration (1/2) (A) Internal non-maskable interrupt
Internal bus
Interrupt request
Priority controller
Vector table address generator
Standby release signal
(B) Internal maskable interrupt
Internal bus
MK
IE
PR
ISP
Interrupt request
IF
Priority controller
Vector table address generator
Standby release signal
(C) External maskable interrupt (INTP0, INTP1)
Internal bus
External interrupt rising/falling edge enable register (EGP, EGN)
MK
IE
PR
ISP
Internal request
Edge detector
IF
Priority controller
Vector table address generator
Standby release signal
22
Data Sheet U13415EJ2V0DS
PD780232
Figure 6-1. Basic Interrupt Function Configuration (2/2) (D) Software interrupt
Internal bus
Interrupt request
Priority controller
Vector table address generator
Data Sheet U13415EJ2V0DS
23
PD780232
7. STANDBY FUNCTION
The standby function is a function to reduce the current consumption. The following two types of standby functions are available. * HALT mode: * STOP mode: Halts the CPU operating clock and enables a reduction in the average current consumption by intermittent operation with normal operation. Halts the system clock oscillation. Halts all operations with the system clock and sets an ultralow power consumption state. Figure 7-1. Standby Function
System clock operation
Interrupt request STOP instruction STOP mode (System clock oscillation is stopped) Interrupt request
HALT instruction
HALT mode
(Clock supply to CPU is stopped, and oscillation is maintained)
8. RESET FUNCTION
The following two types of resetting methods are available. * External reset by the RESET input * Internal reset by watchdog timer loop detection
9. MASK OPTION
The mask options for the PD780232 are shown in Table 9-1. Table 9-1. Pin Mask Option Selection
Pin Name FIP 0 to FIP23, P30/FIP24 to P37/FIP31, P40/FIP32 to P47/FIP39 P50/FIP40 to P57/FIP47, P60/FIP48 to P64/FIP52 Mask Option An on-chip pull-down resistor can be specified for VLOAD in 1-bit units.
An on-chip pull-down resistor can be specified for VLOAD or VSS0 in 1-bit units.
24
Data Sheet U13415EJ2V0DS
PD780232
10. INSTRUCTION SET
(1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
2nd Operand #byte 1st Operand A ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB SUBC AND OR XOR CMP DBNZ MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV DBNZ INC DEC MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP A rNote sfr saddr !addr16 PSW [DE] [HL] [HL+byte] [HL+B] $addr16 [HL+C] MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
1 ROR ROL RORC ROLC
None
r
MOV
INC DEC
B, C sfr saddr
!addr16 PSW [DE] [HL] [HL+byte] [HL+B] [HL+C] X C MOV
MOV MOV MOV MOV MOV ROR4 ROL4 PUSH POP
MULU DIVUW
Note Except r = A
Data Sheet U13415EJ2V0DS
25
PD780232
(2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand #word 1st Operand AX ADDW SUBW CMPW MOVW MOVWNote MOVW XCHW MOVW MOVW MOVW MOVW AX rpNote sfrp saddrp !addr16 SP None
rp
INCW DECW PUSH POP
sfrp saddrp !addr16 SP
MOVW MOVW
MOVW MOVW MOVW
MOVW
MOVW
Note Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd Operand A.bit 1st Operand A.bit MOV1 BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 NOT1 sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None
sfr.bit
MOV1
saddr.bit
MOV1
PSW.bit
MOV1
[HL].bit
MOV1
CY
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
26
Data Sheet U13415EJ2V0DS
PD780232
(4) Call instruction/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
2nd Operand AX 1st Operand Basic instruction BR CALL BR CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ !addr16 !addr11 [addr5] $addr16
Compound instruction
(5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
Data Sheet U13415EJ2V0DS
27
PD780232
11. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Symbol VDD VLOAD AVDD AVSS Input voltage VI1 VI2 Output voltage VO1 VO2 Analog input voltage Output current, high VAN IOH ANI0 to ANI3 Analog input pins P00 to P02, P20 to P27, X1, X2, RESET P50 to P57, P60 to P64 P-ch open drain Conditions Rating -0.3 to +6.5 VDD - 45 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +0.3 -0.3 to VDD + 0.3 VDD - 45 to VDD + 0.3 -0.3 to VDD + 0.3 VDD - 45 to VDD + 0.3 AVSS to AVDD -10 -30 -30 -300 -120 10 5 20 10 700 500 -40 to +85 -40 to +150 Unit V V V V V V V V V mA mA mA mA mA mA mA mA mA mW mW C C
Per pin for P00 to P02 and P20 to P27 Total for P00 to P02 and P20 to P27 Per pin for FIP0 to FIP23, P30 to P37, P40 to P47, P50 to P57, and P60 to P64 Total for FIP0 to FIP23, P30 to P37, P40 to P47, Peak value rms value Peak value rms value Total for P00 to P02 and P20 to P27 Peak value rms value
Output current, low
IOLNote 1
P50 to P57, and P60 to P64 Per pin for P00 to P02 and P20 to P27
Total power dissipation Operating ambient temperature Storage temperature
PTNote 2
TA = -40 to +60C TA = +60 to +85C
TA Tstg
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Notes 1. The rms value should be calculated as follows: [rms value] = [Peak value] x Duty
28
Data Sheet U13415EJ2V0DS
PD780232
Notes 2. The allowable total power dissipation differs depending on the temperature (see the following figure).
Total power dissipation PT [mW]
800
600 500 400
200
-40
0
+40 Temperature [C]
+80 +85
How to calculate total power dissipation The power consumption of the PD780232 can be divided to the following three types. The sum of the three power consumption types should be less than the total power dissipation PT (80% or less of ratings is recommended). <1> <2> <3> CPU power consumption: Calculate VDD (MAX.) x IDD (MAX.). Output pin power consumption: Power consumption when maximum current flows to VFD output pins. Pull-down resistor power consumption: Power consumption by the pull-down resistors incorporated in the VFD output pins by a mask option.
The following shows how to calculate total power consumption for the example in Figure 11-1. Example Assume the following conditions: VDD = 5.5 V, 5.0 MHz oscillation Supply current (IDD) = 21.0 mA VFD output: 11 grids x 10 segments (blanking width = 1/16) The maximum current at the grid pin is 15 mA. The maximum current at the segment pin is 5 mA. At the key scan timing, the VFD output pin is OFF. VFD output voltage: Grids VOD = VDD - 2 V (voltage drop of 2 V) Segments VOD = VDD - 0.5 V (voltage drop of 0.5 V) Fluorescent display control voltage (VLOAD) = -35 V Mask option pull-down resistor = 35 k
Data Sheet U13415EJ2V0DS
29
PD780232
By placing the above conditions in calculations <1> to <3>, the total dissipation can be calculated. <1> CPU power consumption: 5.5 V x 21.0 mA = 115.5 mW <2> Output pin power consumption: Total current value of each grid Number of grids + 1 1 16
Grid
(VDD - VOD) x
x (1 - Blanking width)
= 2Vx
15 mA x 11 grids 11 grids + 1
x (1 -
) = 25.8 mW
Segment
(VDD - VOD) x
Total segment current value of illuminated dots Number of grids +1 1 16
x (1 - Blanking width)
= 0.5 V x
5 mA x 31 dots 11 grids + 1
x (1 -
) = 6.1 mW
<3> Pull-down resistor power consumption: (VOD - VLOAD)2 Pull-down resistor value (5.5 V - 2 V - (-35 V))2 35 k (VOD - VLOAD)2 Pull-down resistor value Number of grids Number of grids + 1 11 grids 11 grids + 1 1 16
Grid
x
x (1 - Blanking width)
=
x
x (1 -
) = 36.4 mW
Segment
x
Number of illuminated dots Number of grids + 1 31 dots 11 grids + 1 1 16
x (1 - Blanking width)
=
(5.5 V - 0.5 V - (-35 V))2 35 k
x
x (1 -
) = 110.7 mW
Total power consumption = <1> + <2> + <3> = 115.5 + 25.8 + 6.1 + 36.4 + 110.7 = 294.5 mW In this example, the total power consumption does not exceed the rating of the allowable total power dissipation, so there is no problem in the power consumption. However, when the total power consumption exceeds the rating of the total power dissipation, it is necessary to lower the power consumption. To reduce the power consumption, reduce the number of pull-down resistors.
30
Data Sheet U13415EJ2V0DS
PD780232
Figure 11-1. Display Example of 10 Segments-11 Digits
Display data memory FA02H, FA01H, FA00H FA09H, FA08H, FA07H FA10H, FA0FH, FA0EH FA17H, FA16H, FA15H FA1EH, FA1DH, FA1CH FA25H, FA24H, FA23H FA2CH, FA2BH, FA2AH FA33H, FA32H, FA31H FA3AH, FA39H, FA38H FA41H, FA40H, FA3FH FA48H, FA47H, FA46H 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 0 1 0 1 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
(VFD output pin: 20 19 18 17 16 15 14 13 12 11 10 FIP0 to FIP20) j ihgfedcba
9
8
7
6
5
4
3
2
1
0
SUN i AM PM 0 i j 1
MON
TUE j j
WED
THU
FRI
SAT f e
a g d 10 b c h
2
3
4
5
6
7
8
9
Data Sheet U13415EJ2V0DS
31
PD780232
System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 4.5 to 5.5 V)
Resonator Ceramic resonator
VSS1 X1 X2
Recommended Circuit
Parameter Oscillation frequency (fX)Note 1
Conditions VDD = Oscillation voltage range
MIN. TYP. MAX. Unit 1 5 MHz
C1
C2
Oscillation stabilization After VDD reaches timeNote 2 the minimum value of oscillation voltage range Oscillation frequency (fX)Note 1 Oscillation stabilization timeNote 2 X1 input frequency (fX)Note 1 X1 input high-/low-level width (tXH/tXL) 1 1
4
ms
Crystal resonator
VSS1 X1 X2
5
MHz
C1
C2
10
ms
External clock
X1 X2
5
MHz
85
450
ns
PD74HCU04
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP release. Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS1. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator.
32
Data Sheet U13415EJ2V0DS
PD780232
Recommended Oscillator Constant
System Clock: Ceramic Resonator (TA = -40 to +85C)
Manufacturer Part Number Frequency (MHz) 1.00 2.00 Recommended Circuit Constant C1 (pF) 150 100 On-chip 3.58 30 On-chip C2 (pF) 150 100 On-chip 30 On-chip Oscillation Voltage Range MIN. (V) 4.5 MAX. (V) 5.5
Murata Mfg. Co., Ltd.
CSB 1000J CSA2.00MG040 CST2.00MG040 CSA3.58MG CST3.58MGW CSTS0358MG06 CSA4.19MG CST4.19MGW CSTS0419MG06 CSA5.00MG CST5.00MGW CSTS0500MG03
4.19
30 On-chip
30 On-chip
5.00
30 On-chip
30 On-chip
Caution
The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation must be adjusted on the implementation circuit. For details, please contact directly the manufacturer of the resonator you will use.
Data Sheet U13415EJ2V0DS
33
PD780232
Capacitance (TA = 25C, VDD = VSS = 0 V)
Parameter Input capacitance Symbol CIN Conditions f = 1 MHz P00 to P02, P20 to P27 Unmeasured pins returned to 0 V P50 to P57, P60 to P64 f = 1 MHz P00 to P02, P20 to P27 Unmeasured pins returned to 0 V P30 to P37, P40 to P47, P50 to P57, P60 to P64, FIP0 to FIP23 I/O capacitance CIO f = 1 MHz P00 to P02, P20 to P27 Unmeasured pins returned to 0 V P50 to P57, P60 to P64 15 35 pF pF MIN. TYP. MAX. 15 35 15 35 Unit pF pF pF pF
Output capacitance
COUT
DC Characteristics (TA = -40 to +85C, VDD = 4.5 to 5.5 V)
Parameter Input voltage, high Symbol VIH1 VIH2 VIH3 Input voltage, low VIL1 VIL2 Output voltage, high VOH Conditions P00 to P02, P20 to P27, RESET P50 to P57, P60 to P64 X1, X2 P00 to P02, P20 to P27, RESET X1, X2 IOH = -1 mA IOH = -100 A Output voltage, low Input leakage current, high Input leakage current, low VOL ILIH1 ILIH2 ILIL1 ILIL2 ILIH3 Output leakage current, high Output leakage current, low VFD output current ILOH ILOL1 ILOL2 IOD P00 to P02, P20 to P27 P00 to P02, P20 to P27, P50 to P57, P60 to P64, RESET X1, X2 P00 to P02, P20 to P27, RESET X1, X2 P50 to P57, P60 to P64 P00 to P02, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P64 P00 to P02, P20 to P27 VIN = VLOAD = VDD - 40 V VOUT = VDD VOUT = 0 V VIN = 0 V IOL = 400 A VIN = VDD MIN. 0.7VDD 0.7VDD VDD - 0.5 0 0 VDD - 1.0 VDD - 0.5 TYP. MAX. VDD VDD VDD 0.2VDD 0.4 VDD VDD 0.5 3 20 -3 -20 -10 3 -3 -10 -15 -5 VIN = 0 V 10 15 30 35 100 90 Unit V V V V V V V V
A A A A A A A A
mA mA k k
P30 to P37, P40 to P47, P50 to P57, P60 to P64 VOUT = VLOAD = VDD - 40 V FIP0 to FIP19 FIP20 to FIP52 VOD = VDD - 2 V
Software pull-up resistance On-chip mask option pull-down resistance (VSS0 connection) On-chip mask option pull-down resistance (VLOAD connection) Power supply currentNote
R1 R2
P00 to P02, P20 to P27 P50 to P57, P60 to P64
R3
FIP0 to FIP52
VOD - VLOAD = 40 V PCC = 00H
30
60
135
k
IDD1 IDD2 IDD3
5 MHz crystal oscillation operation mode 5 MHz crystal oscillation HALT mode STOP mode
7 1.5 1
14 4.5 30
mA mA
A
Note Refers to the current flowing to the VDD pin. The current flowing to the on-chip pull-up and pull-down resistors is not included. Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 2. PCC: Processor clock control register
34
Data Sheet U13415EJ2V0DS
PD780232
AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 4.5 to 5.5 V)
Parameter Cycle time (minimum instruction execution time) Interrupt request input high-/low-level width RESET low-level width tINTH tINTL tRSL INTP0, INTP1 10 Symbol TCY Conditions Operated with main system clock MIN. 0.4 TYP. MAX. 32 Unit
s
s
10
s
TCY vs. VDD
60 30
10
Cycle time TCY (s)
2.0 1.0
0.5 0.4
0
1
2
3
4
5
Guaranteed operating range
6
Supply voltage VDD (V)
(2) Timer/counter (TA = -40 to +85C, VDD = 4.5 to 5.5 V)
Parameter TI input high-/ low-level width Symbol tTIH tTIL Conditions MIN. 2/Fcount + 0.2Note TYP. MAX. Unit
s
Note FCOUNT is the frequency of the count clock selected by TM9 (the frequency can be selected from fX/26, fX/27, fX/28, and fX/29).
Data Sheet U13415EJ2V0DS
35
PD780232
(3) Serial interface (TA = -40 to +85C, VDD = 4.5 to 5.5 V) (a) Serial interface (3-wire serial mode) (i) 3-wire serial mode (SCK1: Internal clock output)
Symbol tKCY1 Conditions MIN. 800 tKCY1/2 - 50 100 400 C = 100 pFNote 300 TYP. MAX. Unit ns ns ns ns ns
Parameter SCK1 cycle time
SCK1 high-/low-level tKH1 width tKL1 SI1 setup time (to SCK1) SI1 hold time (from SCK1) tSIK1 tKSI1
Delay time from SCK1 tKSO1 to SO1 output
Note C is the load capacitance of the SCK1 and SO1 output lines. (ii) 3-wire serial mode (SCK1: External clock input)
Parameter SCK1 cycle time SCK1 high-/lowlevel width SI1 setup time (to SCK1) SI1 hold time (from SCK1) Delay time from SCK1 tKSO2 to SO1 output SCK1 rise/fall time tR2 tF2 C = 100 pFNote 300 1 ns Symbol tKCY2 tKH2 tKL2 tSIK2 tKSI2 100 400 ns ns Conditions MIN. 800 400 TYP. MAX. Unit ns ns
s
Note C is the load capacitance of the SO1 output line.
36
Data Sheet U13415EJ2V0DS
PD780232
(b) Serial interface (2-wire serial mode) (i) 2-wire serial mode (SCK3...Internal clock output)
Symbol tKCY3 tKH3 tKL3 tKSO3 C = 100 pFNote Conditions MIN. 800 tKCY3/2 - 50 300 TYP. MAX. Unit ns ns ns
Parameter SCK3 cycle time SCK3 high-/low-level width Delay time from SCK3 to SO3 output
Note C is the load capacitance of the SCK3 and SO3 output lines. (ii) 2-wire serial mode (SCK3...External clock input)
Parameter SCK3 cycle time SCK3 high-/lowlevel width Delay time from SCK3 to SO3 output SCK3 rise/fall time Symbol tKCY4 tKH4 tKL4 tKSO4 tR4 tF4 C = 100 pFNote Conditions MIN. 800 400 300 1 TYP. MAX. Unit ns ns ns
s
Note C is the load capacitance of the SO3 output line.
Data Sheet U13415EJ2V0DS
37
PD780232
AC Timing Test Points (Excluding X1 Input)
0.8VDD Test points 0.2VDD
0.8VDD 0.2VDD
Clock Timing
1/fX tXL tXH
X1 input
VDD - 0.5 V (MIN.) 0.4 V (MAX.)
TI Timing
tTIL
tTIH
TI
38
Data Sheet U13415EJ2V0DS
PD780232
Serial Transfer Timing 3-wire serial mode:
tKCY1, 2
tKL1, 2 tR2 SCK1 tSIK1, 2 tKSI1, 2
tKH1, 2 tF2
SI1 tKSO1, 2
Input data
SO1
Output data
2-wire serial mode:
tKCY3,4 tKL3,4 tR4 SCK3 tKSO3,4 tKH3,4 tF4
SO3
A/D Converter Characteristics (TA = -40 to +85C, AVDD = VDD = 4.0 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Overall errorNote 1 timeNote 2 tCONV VIAN 14 AVSS AVDD Symbol Conditions MIN. TYP. MAX. 8 1.0 Unit bit %
Conversion
s
V
Analog input voltage
Notes 1. Quantization error (1/2LSB) is not included. This parameter is indicated as the ratio to the full-scale value. 2. Set the A/D conversion time to 14 s or more.
Data Sheet U13415EJ2V0DS
39
PD780232
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C)
Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillation stabilization wait time tWAIT Release by RESET Release by interrupt request 217/fX Note ms ms IDDDR tSREL 0 0.1 30 Symbol VDDDR Conditions MIN. 2.0 TYP. MAX. 5.5 Unit V
A s
Note 212/fX, 214/fX to 217/fX can be selected by bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS). Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation HALT mode STOP mode Data retention mode Operating mode
VDD STOP instruction execution
VDDDR
tSREL
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)
HALT mode STOP mode Data retention mode Operating mode
VDD STOP instruction execution
VDDDR
tSREL
Standby release signal (interrupt request) tWAIT
40
Data Sheet U13415EJ2V0DS
PD780232
Interrupt Request Input Timing
tINTL
tINTH
INTP0, INTP1
RESET Input Timing
tRSL
RESET
Data Sheet U13415EJ2V0DS
41
PD780232
12. PACKAGE DRAWING
80-PIN PLASTIC QFP (14x14)
A B
60 61
41 40
detail of lead end S C D R Q
80 1
21 20
F J G P H I
M
K S N S L M
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 17.200.20 14.000.20 14.000.20 17.200.20 0.825 0.825 0.320.06 0.13 0.65 (T.P.) 1.600.20 0.800.20 0.17 +0.03 -0.07 0.10 1.400.10 0.1250.075 3 +7 -3 1.70 MAX. P80GC-65-8BT-1
NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.
42
Data Sheet U13415EJ2V0DS
PD780232
13. RECOMMENDED SOLDERING CONDITIONS
The PD780232 should be soldered and mounted under the following recommended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 13-1. Surface Mounting Type Soldering Conditions
PD780232GC-xxx-8BT: 80-pin plastic QFP (14 x 14)
Soldering Infrared reflow VPS Wave soldering Partial heating Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Two times or less Solder bath temperature: 260C max., Time: 10 seconds max., Count: once, Preheating temperature: 120C max. (package surface temperature) Pin temperature: 300C max., Time: 3 seconds max. (per pin row) -- Recommended Method Condition Symbol IR35-00-2 VP15-00-2 WS60-00-1
Caution
Do not use different soldering methods together (except for partial heating).
Data Sheet U13415EJ2V0DS
43
PD780232
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD780232. Also refer to (6) Notes on using development tools. (1) Software Package
SP78K0 Software package common to 78K/0 Series
(2) Language Processing Software
RA78K0 CC78K0 DF780233 CC78K0-L Assembler package common to 78K/0 Series C compiler package common to 78K/0 Series Device file for PD780232 Subseries C compiler library source file common to 78K/0 Series
(3) Flash Memory Writing Tools
Flashpro III (FL-PR3, PG-FP3) FA-80GC Dedicated flash programmer for on-chip flash memory microcontrollers Adapter for flash memory writing. Used by connecting to Flashpro III. * For 80-pin plastic QFP (GC-8BT type)
(4) Debugging Tools * When in-circuit emulator IE-78K0-NS(-A) is used
IE-78K0-NS(-A) IE-70000-MC-PS-B IE-78K0-NS-PA IE-70000-98-IF-C IE-70000-CD-IF-A IE-70000-PC-IF-C IE-70000-PCI-IF-A IE-780233-NS-EM4, IE-78K0-NS-P01 NP-80GC NP-80GC-TQ NP-H80GC-TQ EV-9200GC-80 TGC-080SBP ID78K0-NS SM78K0 DF780233 In-circuit emulator common to 78K/0 Series Power supply unit for IE-78K0-NS Performance board to enhance/extend the functions of the IE-78K0-NS Adapter required when PC-9800 series (except notebook type) is used as host machine (C bus supported) PC card and interface cable required when notebook-type PC is used as host machine (PCMCIA socket supported) Adapter required when IBM PC/ATTM compatible is used as host machine (ISA bus supported) Adapter required when PC incorporating PCI bus is used as host machine Emulation board and I/O board to emulate the PD780232 Subseries Emulation probe for 80-pin plastic QFP (GC-8BT type)
Conversion socket to connect the NP-80GC and the target system board on which 80-pin plastic QFP (GC-8BT type) can be mounted Conversion adapter to connect the NP-80GC-TQ or NP-H80GC-TQ and the target system board on which 80-pin plastic QFP (GC-8BT type) can be mounted Integrated debugger for IE-78K0-NS System simulator common to 78K/0 Series Device file for PD780232 Subseries
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Data Sheet U13415EJ2V0DS
PD780232
* When in-circuit emulator IE-78001-R-A is used
IE-78001-R-A IE-70000-98-IF-C IE-70000-PC-IF-C IE-70000-PCI-IF-A IE-70000-R-SV3 IE-780233-NS-EM4, IE-78K0-NS-P01 IE-78K0-R-EX1 EP-78230GC-R EV-9200GC-80 ID78K0 SM78K0 DF780233 In-circuit emulator common to 78K/0 Series Adapter required when PC-9800 series (except notebook type) is used as host machine (C bus supported) Adapter required when IBM PC/AT compatible is used as host machine (ISA bus supported) Adapter required when PC incorporating PCI bus is used as host machine Interface adapter and cable required when EWS is used as host machine Emulation board and I/O board to emulate the PD780232 Subseries Emulation probe conversion board required when using IE-780232-NS-EM1 on IE-78001-R-A Emulation probe for 80-pin plastic QFP (GC-8BT type) Conversion socket to connect the EP-78230GC-R and the target system board on which 80-pin plastic QFP (GC-8BT type) can be mounted Integrated debugger for IE-78001-R-A System simulator common to 78K/0 Series Device file for PD780232 Subseries
(5) Real-Time OSs
RX78K0 MX78K0 Real-time OS for 78K/0 Series OS for 78K/0 Series
Data Sheet U13415EJ2V0DS
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PD780232
(6) Notes on using development tools * The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780233. * The CC78K0 and RX78K0 are used in combination with the RA78K0 and DF780233. * The FL-PR3, FA-80GC, NP-80GC, NP-80GC-TQ, and NP-H80GC-TQ are products of Naito Densei Machida Mfg. Co., Ltd (+81-45-475-4191). * The TGK-080SBP is a product made by TOKYO ELETECH CORPORATION. For further information, contact: Daimaru Kogyo, Ltd. Tokyo Electronics Department (TEL +81-3-3820-7112) Osaka Electronics Department (TEL +81-6-6244-6672) * For third-party development tools, see the Single-Chip Microcontroller Development Tool Selection Guide (U11069E). * The host machines and OS suitable for each software are as follows:
Host Machine [OS] Software RA78K0 CC78K0 ID78K0-NS ID78K0 SM78K0 RX78K0 MX78K0 PC PC-9800 series [Japanese WindowsTM] IBM PC/AT compatibles [Japanese/English Windows] Note Note Note Note EWS HP9000 series 700TM [HP-UXTM] SPARCstationTM [SunOSTM, SolarisTM] -- -- --
Note DOS-based software
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Data Sheet U13415EJ2V0DS
PD780232
APPENDIX B. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices
Document Name Document No. U13364E This manual U13322E U12326E U14458E
PD780232 Subseries User's Manual PD780232 Data Sheet PD78F0233 Data Sheet
78K/0 Series Instructions User's Manual 78K/0, 78K/0S Series Flash Memory Write Application Note
Documents Related to Development Tools (User's Manuals)
Document Name RA78K0 Assembler Package Operation Language Structured Assembly Language CC78K0 C Compiler Operation Language PG-FP3 Flash Memory Programmer IE-78K0-NS In-Circuit Emulator IE-78K0-NS-A In-Circuit Emulator IE-78001-R-A In-Circuit Emulator IE-78K0-R-EX1 In-Circuit Emulator IE-780233-NS-EM4 Emulation Board EP-78230 Emulation Probe SM78K0S, SM78K0 System Simulator Ver. 2.10 or Later Windows Based SM78K Series System Simulator Ver. 2.10 or Later ID78K0-NS Integrated Debugger Ver. 2.00 or Later Windows Based ID78K0-NS, ID78K0S-NS Integrated Debugger Ver. 2.20 or Later Windows Based ID78K0 Integrated Debugger Windows Based Operation External Parts User Open Interface Specifications Operation Operation Guide Reference Document No. U14445E U14446E U11789E U14297E U14298E U13502E U13731E U14889E U14142E To be prepared U14666E EEU-1515 U14611E U15006E U14379E U14910E U11649E U11539E
Data Sheet U13415EJ2V0DS
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PD780232
Documents Related to Embedded Software (User's Manuals)
Document Name 78K/0 Series Real-time OS Fundamentals Installation 78K/0 Series OS MX78K0 Fundamentals Document No. U11537E U11536E U12257E
Other Documents
Document Name SEMICONDUCTOR SELECTION GUIDE - Products & Package - (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Document No. X13769E C10535E C11531E C10983E C11892E
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
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Data Sheet U13415EJ2V0DS
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[MEMO]
Data Sheet U13415EJ2V0DS
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PD780232
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
FIP and IEBus are trademarks of NEC Corporation. Windows is either a registered trademark or trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc.
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Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 253-8311 Fax: 250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829
J01.2
Data Sheet U13415EJ2V0DS
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PD780232
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
* The information in this document is current as of February, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
M8E 00.4

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